Electronics

    ⭐⭐⭐⭐⭐   Newsletter: #FPGA (Field Programmable Gate Arrays) ➡️  #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA ⭐  https://github.com/VHDL-Digital-Systems ⭐ When using this resource, please cite the original publication: Montesdeoca, G., Asanza, V., Estrada, R., Valeriano, I., Muneeb, M.A. (2023). Softprocessor RISCV-EC for Edge Computing Applications.  In: Barolli, L. (eds) Innovative Mobile and Internet Services in Ubiquitous Computing . IMIS 2023. Lecture Notes on Data Engineering and Communications Technologies, vol 177. Springer, Cham. https://doi.org/10.1007/978-3-031-35836-4_23 FPGAs (Field-Programmable Gate Arrays) are programmable electronic devices that allow for the creation of customized digital circuits. Unlike ASICs (Application-Specific Integrated Circuits), which are integrated circuits specifically designed for one application, FPGAs can be programmed and reprogrammed to perform different tasks. ➡️ One of the mo...

⭐⭐⭐⭐⭐ #BCI System using a Novel Processing Technique Based on Electrodes Selection for Hand #Prosthesis Control from Victor Asanza ➡️ #EEG #Classification #HumanMachineInterface #BCI #BrainComputerInterface #Emotiv ✅ #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA ➡️ BMS2021:  11th IFAC Symposium on Biological and Medical Systems #BMS2021 ➡️  Presented by: Alisson Constantine ➡️ When using this resource, please cite the original publication: Constantine, A., Asanza, V., Loayza, F. R., Peláez, E., & Peluffo-Ordóñez, D. (2021). BCI System using a Novel Processing Technique Based on Electrodes Selection for Hand Prosthesis Control.  IFAC-PapersOnLine, 54(15), 364-369. ✅  Abstract: This work proposes an end-to-end model architecture, from feature extraction to classification using an Artificial Neural Network. The feature extraction process starts from an initial set of signals acquired by electrodes of a Brain-Computer Interface (BCI)...

⭐⭐⭐⭐⭐ Performance Comparison of Database Server based on #SoC #FPGA and #ARM Processor from Victor Asanza ➡️ #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA ➡️  2021 IEEE Latin-American Conference on Communications #LATINCOM ➡️  Presented by: Rebeca Estrada ⭐  Read full paper:  https://ieeexplore.ieee.org/document/9647742 ⭐  Source code repository:  https://github.com/VHDL-Digital-Systems/Sistema_gestion_base_de_datos_FPGA_HPS_DE10Standard When using this resource, please cite the original publication: V. Asanza, R. Estrada, J. Miranda, L. Rivas and D. Torres, "Performance Comparison of Database Server based on SoC FPGA and ARM Processor," 2021 IEEE Latin-American Conference on Communications (LATINCOM), 2021, pp. 1-6, doi: 10.1109/LATINCOM53176.2021.9647742. ✅ Video of the talk: ✅ Conference content: Published in Introduction Dataset Methodology Results Conclusions Repository For more information ✅  References: Tun, S. ...

⭐⭐⭐⭐⭐ SOLUCIÓN EXAMEN SISTEMAS DIGITALES 2, 1er Parcial (2021PAO2) from Victor Asanza ➡️  #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA ⭐  https://github.com/vasanza/MSI-VHDL Repositorio con los archivos VHDL de la pregunta: https://github.com/vasanza/DigitalSystems/tree/2021PAO2/2021_PAO2_1P_Examen La siguiente partición funcional que incluye una Maquina Secuencial Sincrónica (MSS) y tres registros de sostenimiento, debe realizar el ingreso de datos a cada uno de los registros y luego permitirá encontrar el valor máximo y mínimo ingresado. Además, cada uno de los registros indicados es de 8 bits para mostrar los valores encontrados de máximo (Qmax) y mínimo (Qmin) serán de 8 bits cada uno. El sistema digital funciona con una MSS modelo Moore de la siguiente forma: La MSS luego de ser reiniciado empieza en el estado inicial. El Sistema Digital en el estado inicial, esperará que el usuario presione y suelte la tecla Start dos veces, luego de lo cual ...