Electronics

    ⭐⭐⭐⭐⭐   Newsletter: #FPGA (Field Programmable Gate Arrays) ➡️  #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA ⭐  https://github.com/VHDL-Digital-Systems ⭐ When using this resource, please cite the original publication: Montesdeoca, G., Asanza, V., Estrada, R., Valeriano, I., Muneeb, M.A. (2023). Softprocessor RISCV-EC for Edge Computing Applications.  In: Barolli, L. (eds) Innovative Mobile and Internet Services in Ubiquitous Computing . IMIS 2023. Lecture Notes on Data Engineering and Communications Technologies, vol 177. Springer, Cham. https://doi.org/10.1007/978-3-031-35836-4_23 FPGAs (Field-Programmable Gate Arrays) are programmable electronic devices that allow for the creation of customized digital circuits. Unlike ASICs (Application-Specific Integrated Circuits), which are integrated circuits specifically designed for one application, FPGAs can be programmed and reprogrammed to perform different tasks. ➡️ One of the mo...

 ⭐⭐⭐⭐⭐ Zynq UltraScale+ MPSoC ➡️  #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA ⭐  https://github.com/vasanza/MSI-VHDL Los dispositivos Zynq® UltraScale+™ MPSoC ofrecen escalabilidad de procesador de 64 bits a la vez que combinan el control en tiempo real con motores blandos y duros para el procesamiento de gráficos, vídeo, formas de onda y paquetes. Construidos sobre una plataforma común de procesador en tiempo real y lógica programable, tres variantes distintas incluyen dispositivos de doble procesador de aplicaciones (CG), dispositivos de cuádruple procesador de aplicaciones y GPU (EG), y dispositivos de códec de vídeo (EV), creando posibilidades ilimitadas para aplicaciones como 5G Wireless, ADAS de próxima generación e Internet de las cosas industrial. Zynq UltraScale+ EV Video Codec Enabled for Multimedia and Embedded Vision Quad Arm Cortex-A53 Dual Arm Cortex-R5F 16nm FinFET+ Programmable Logic Arm Mali-400MP2 H.264/H.265 Video Codec Genesys ...

  ⭐⭐⭐⭐⭐  #FPGA # Xilinx #Virtex UltraScale+ VCU128 ➡️  #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA ⭐  https://github.com/VHDL-Digital-Systems The #RISC_V architecture has broken a new record in the CoreScore benchmark, and it did so with #Xilinx's most powerful #FPGA, the Virtex UltraScale+ VCU128, which hides no less than 6,000 SERV cores under a single package, so it is not surprising that the previous record was held by the VCU118 with 5,087 cores. This number of cores is close to the maximum that the silicon is capable of delivering, as it is indicated that 98.5 percent of the available space is being occupied. Basically, this benchmark is born, literally, to see who is able to integrate more SERV cores in an #FPGA, so do not expect performance details and even less to see it in a gaming benchmark or running Crysis. ➡️  Source:  https://elchapuzasinformatico.com/2021/09/xilinx-virtex-ultrascale-vcu128-record-mundial-en-corescore...

  ⭐⭐⭐⭐⭐  Maximum to minimum ordering of values in #RAM memory using #VHDL ➡️  #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA The following functional partition, which includes a Machine Sequential Synchronous (MSS), must perform a sorting of 255 values from Highest to Lowest. The entry of these 8-bit values must be done one by one, these values are entered through the "Data" port, while the data is being entered, the MSS sets high the "WritingData" output, indicating that this process is being executed and it will not end until the 255 values are completed. The ordering of the previously entered numbers should be done from highest to lowest, for which it is recommended to use the counter_up "j" and counter_up "i" in the search and comparison process. It is requested: Perform the functional partitioning Draw the ASM diagram of the MSS controller. Create in Quartus the Block diagram Schematic file Simulate the operation of the...

⭐⭐⭐⭐⭐ SOLUCIÓN EVALUACIÓN SISTEMAS DIGITALES 1, 1er Parcial (2021 PAO1) from Victor Asanza   ➡️  #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA ⭐  https://github.com/vasanza/MSI-VHDL ✅ Problema #1 (x%) . El siguiente es un Sistema Digital que tiene las señales ‘A’,’ B’, ‘C’ y ‘D’ como entradas de un bit; por otro lado, la señal ‘Y’ es una salida de un bit tal como se muestra en la siguiente imagen: El comportamiento de la señal de salida ‘Y’ en función de las señales de entrada, es descrito con el siguiente código VHDL: ⭐  Código GitHub: https://github.com/vasanza/MSI-VHDL/blob/2021PAO1/ExamenParcial/ExamSD1_1.vhd Realizar los siguientes desarrollos: a) Usando mapas de karnaught y agrupamiento de minterms (SOP), simplificar la expresión booleana hasta obtener su minima expresión (x/2 %). b) Utilizando puertas lógicas, graficar el circuito que represente a la ecuación simplificada en el literal anterior (x/2 %). Resolución: a) b) ✅ ...

 ⭐⭐⭐⭐⭐ Maximum number finder and repetition counter (VHDL Functional Partition) ➡️  #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA In this functional partition example, it performs the following tasks: Allows entry of up to 255 4-bit numbers Then search for the highest number and indicate the number of times it is repeated The software used was Quartus Prime 19.1 Repository with VHDL codes: https://github.com/vasanza/DigitalSystems/tree/2021PAO1/Ejemplo3_BuscadorMaxRep Functional Partition PDF: https://github.com/vasanza/DigitalSystems/blob/2021PAO1/Ejemplo3_BuscadorMaxRep/notasclase.pdf Read related topics ✅ #FPGA projects for Engineering Students Phrases recognition with Machine Learning #ML (InnovateFPGA) Example: Access control system (2) Example: Access control system (1) ✅ 2020 Paper: Monitoring of system memory usage embedded in #FPGA ✅ 2020 Paper: Implementation of a Classification System of #EEG Signals Based on #FPGA ✅ 2020 Paper: Behavioral Sig...