Electronics

  ⭐⭐⭐⭐⭐  #FPGA # Xilinx #Virtex UltraScale+ VCU128 ➡️  #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA ⭐  https://github.com/VHDL-Digital-Systems The #RISC_V architecture has broken a new record in the CoreScore benchmark, and it did so with #Xilinx's most powerful #FPGA, the Virtex UltraScale+ VCU128, which hides no less than 6,000 SERV cores under a single package, so it is not surprising that the previous record was held by the VCU118 with 5,087 cores. This number of cores is close to the maximum that the silicon is capable of delivering, as it is indicated that 98.5 percent of the available space is being occupied. Basically, this benchmark is born, literally, to see who is able to integrate more SERV cores in an #FPGA, so do not expect performance details and even less to see it in a gaming benchmark or running Crysis. ➡️  Source:  https://elchapuzasinformatico.com/2021/09/xilinx-virtex-ultrascale-vcu128-record-mundial-en-corescore-con-sus-6-000-nucleos/ R

  ⭐⭐⭐⭐⭐ SSVEP-EEG Signal Classification based on Emotiv EPOC BCI and Raspberry Pi   from  Victor Asanza ➡️ #EEG #Classification #HumanMachineInterface #BCI #BrainComputerInterface #Emotiv ➡️ BMS2021:  11th IFAC Symposium on Biological and Medical Systems #BMS2021 ➡️  Presented by:  Karla Avilés ✅ Repository: https://github.com/kaviles22/EEG_Embedded_Systems ⭐  Read full paper:  https://doi.org/10.1016/j.ifacol.2021.10.287 When using this resource, please cite the original publication: Asanza, V., Avilés-Mendoza, K., Trivino-Gonzalez, H., Rosales-Uribe, F., Torres-Brunes, J., Loayza, F. R., ... & Tinoco-Egas, R. (2021). SSVEP-EEG Signal Classification based on Emotiv EPOC BCI and Raspberry Pi. IFAC-PapersOnLine, 54(15), 388-393. ✅  Abstract: This work presents the experimental design for recording Electroencephalography (EEG) signals in 20 test subjects submitted to Steady-state visually evoked potential (SSVEP). The stimuli were performed with frequencies of 7, 9, 11 and 13 Hz.