⭐⭐⭐⭐⭐ Maximum to minimum ordering of values in #RAM memory using #VHDL

• ➡️ #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA

The following functional partition, which includes a Machine Sequential Synchronous (MSS), must perform a sorting of 255 values from Highest to Lowest. The entry of these 8-bit values must be done one by one, these values are entered through the "Data" port, while the data is being entered, the MSS sets high the "WritingData" output, indicating that this process is being executed and it will not end until the 255 values are completed. The ordering of the previously entered numbers should be done from highest to lowest, for which it is recommended to use the counter_up "j" and counter_up "i" in the search and comparison process. It is requested:

• Perform the functional partitioning
• Draw the ASM diagram of the MSS controller.
• Create in Quartus the Block diagram Schematic file
• Simulate the operation of the complete system in the VWF file.

Functional Partition

ASM Diagram

• ☑️ Repository with VHDL codes:
• https://github.com/vasanza/DigitalSystems/tree/main/Example_MaxToMin_ordering_in_RAM

• ☑️ Functional Partition PDF:
• https://github.com/vasanza/DigitalSystems/blob/main/Example_MaxToMin_ordering_in_RAM/2020_PAO2_2P_Examen(Resuelto).pdf

#VDHL Code by Angel Zumba

• sumador.vhd

  	--https://vasanza.blogspot.com
  	--Library
  	library ieee;
  	use ieee.std_logic_1164.all;
  	use ieee.std_logic_unsigned.all;
  	--Entity
  	entity Sumador is
  	generic ( n: integer :=8);--<------- nbits
  	port(
  	X,Y: in std_logic_vector(n-1 downto 0);
  	S: out std_logic_vector(n downto 0));
  	end Sumador;
  	--Architecture
  	architecture solve of Sumador is
  	-- Signals,Constants,Variables,Components
  	begin
  	s<=('0'&x)+('0'&y);--Without the sign bit
  	--s<='0'&(x+y);--with sign bit
  	end solve;

  view raw Sumador.vhd hosted with ❤ by GitHub

• mss.vhd

  	--https://vasanza.blogspot.com
  	-- By Angel Zumba
  	-- MSS
  	library ieee;
  	use ieee.std_logic_1164.all;
  	entity MSS is
  	port (clk, resetn, start,WriteData, Fin_j, AmenB, Fin_i: in std_logic;
  	enj,ldj,WritingData,s1,eni,ldi,enReg,Sel,enReg2,sel3,sel2,done: out std_logic);
  	end MSS;
  	architecture solv of MSS is
  	type estado is (A,B,C,D,E,F,G,H,I,J,K);
  	signal y: estado;
  	signal entradas: std_logic_vector(4 downto 0);
  	signal salidas: std_logic_vector(11 downto 0);
  	begin
  	entradas <= start & WriteData & Fin_j & AmenB & Fin_i;
  	enj <= salidas(11); ldj <= salidas(10); WritingData <= salidas(9); s1 <= salidas(8); eni <= salidas(7); ldi <= salidas(6); enReg <= salidas(5);
  	Sel <= salidas(4); enReg2 <= salidas(3); sel3 <= salidas(2); sel2 <= salidas(1); done <= salidas(0);
  	process(clk, resetn)
  	begin
  	if resetn = '0' then y <= A;
  	elsif (clk' event and clk = '1') then
  	case y is
  	when A => if entradas = "10000" then y <= B; else y <= A; end if;
  	when B => if entradas = "10000" then y <= B; else y <= C; end if;
  	when C => if entradas = "01000" then y <= D;
  	elsif entradas = "01100" then y<= E;
  	else y <= C; end if;
  	when D => y <= C;
  	when E => if entradas = "00100" then y <= J; else y <= F; end if;
  	when F => y <= G;
  	when G => if entradas = "00010" then y <= H; else y <= I; end if;
  	when H => y <= I;
  	when I => if entradas = "00100" then y <= E; else y <= G; end if;
  	when J => if entradas = "10000" then y <= K; else y <= J; end if;
  	when K => if entradas = "10000" then y <= K; else y <= A; end if;
  	end case;
  	end if;
  	end process;
  	process(y)
  	begin
  	salidas <= "000000000000";
  	case y is
  	when A => salidas <= "110000000000";
  	when C => if entradas = "01100" then salidas <= "111100000000";
  	elsif entradas = "01000" then salidas <= "001100000000";
  	else salidas <= "001000000000"; end if;
  	when D => salidas <= "100000000000";
  	when F => salidas <= "000011100000";
  	when G => if entradas = "00010" then salidas <= "000100011100";
  	else salidas <= "000000011100"; end if;
  	when H => salidas <= "000100000110";
  	when I => if entradas = "00001" then salidas <= "100000000000";
  	else salidas <= "000010000000"; end if;
  	when J => salidas <= "000000000001";
  	when others => salidas <= "000000000000";
  	end case;
  	end process;
  	end solv;

  view raw mss.vhd hosted with ❤ by GitHub

• comparador.vhd

  	--https://vasanza.blogspot.com
  	--Library
  	library ieee;
  	use ieee.std_logic_1164.all;
  	--Entity
  	Entity comparador is
  	generic ( n: integer := 8);--<-- nbits
  	Port(
  	A: in std_logic_vector(n-1 downto 0);
  	B: in std_logic_vector(n-1 downto 0);
  	AmenorB, AmayorB, AigualB: out std_logic);
  	end comparador;
  	--Architecture
  	Architecture solve of comparador is
  	-- Signals,Constants,Variables,Components
  	Begin
  	AmenorB<='1' when A<B else '0';
  	AmayorB<='1' when A>B else '0';
  	AigualB<='1' when A=B else '0';
  	end solve;

  view raw comparador.vhd hosted with ❤ by GitHub

• contador_up.vhd

  	--https://vasanza.blogspot.com
  	--Library
  	library ieee;
  	use ieee.std_logic_1164.all;
  	use ieee.std_logic_unsigned.all;
  	--Entity
  	entity contador_up is
  	generic ( n: integer :=8);--<------- nbits
  	port(
  	Clk,resetn,en,ld: in std_logic;
  	D: in std_logic_vector(n-1 downto 0);
  	q: buffer std_logic_vector(n-1 downto 0));
  	end contador_up;
  	--Architecture
  	architecture solve of contador_up is
  	-- Signals,Constants,Variables,Components
  	begin
  	--Process #1
  	process(resetn,clk)
  	--Sequential programming
  	begin
  	if resetn='0' then
  	q<=(others => '0');
  	elsif clk'event and clk='1' then
  	if en='1' and ld='0' then
  	q<=q+1;
  	elsif en='1' and ld='1' then
  	q<= D;
  	end if;
  	end if;
  	end process;
  	--Process #n...
  	end solve;

  view raw contador_up.vhd hosted with ❤ by GitHub

• mux2a1.vhd

  	--https://vasanza.blogspot.com
  	--Library
  	library ieee;
  	use ieee.std_logic_1164.all;
  	--Entity
  	entity mux2a1 is
  	generic ( n: integer:=8);--<-- nbits
  	port( A: in std_logic_vector(n-1 downto 0);
  	B: in std_logic_vector(n-1 downto 0);
  	Sel: in std_logic;
  	en: in std_logic;
  	Q: out std_logic_vector(n-1 downto 0));
  	end mux2a1;
  	--Architecture
  	architecture solve of mux2a1 is
  	-- Signals,Constants,Variables,Components
  	signal f: std_logic_vector(n-1 downto 0);
  	begin
  	with Sel select
  	f<= A when '0',
  	B when others;
  	Q<= f when en='1' else (others=>'0');
  	end solve;

  view raw mux2a1.vhd hosted with ❤ by GitHub

• ram.vhd

  	--https://vasanza.blogspot.com
  	--Library
  	library ieee;
  	use ieee.std_logic_1164.all;
  	use ieee.std_logic_arith.all;
  	use ieee.std_logic_unsigned.all;
  	--Entity
  	entity ram is
  	generic(n: integer:=8;-- n-bits per data
  	m: integer:=8); -- m-bits of addresses
  	port(
  	clk,wr: in std_logic;
  	addr : in std_logic_vector(m-1 downto 0);
  	Din : in std_logic_vector(n-1 downto 0);
  	Dout : out std_logic_vector(n-1 downto 0));
  	end ram;
  	--Architecture
  	architecture solve of ram is
  	-- Signals,Constants,Variables,Components
  	type ram_type is array (0 to (2**m)-1) of std_logic_vector(n-1 downto 0);
  	signal tmp_ram: ram_type;
  	begin
  	--Process #1:
  	process(clk,wr)
  	--Sequential programming
  	begin
  	if (clk'event and clk='1') then
  	if wr='1' then --write
  	tmp_ram(conv_integer(addr)) <= Din;
  	end if;
  	end if;
  	end process;
  	Dout <= tmp_ram(conv_integer(addr));--read
  	--Process #n...
  	end solve;

  view raw ram.vhd hosted with ❤ by GitHub

• registro.vhd

  	--https://vasanza.blogspot.com
  	--Library
  	library ieee;
  	use ieee.std_logic_1164.all;
  	--Entity
  	entity registro is
  	generic ( n: integer :=8);--<-- nbits
  	port(
  	Clk,resetn,en: in std_logic;
  	d: in std_logic_vector(n-1 downto 0);
  	q: out std_logic_vector(n-1 downto 0));
  	end registro;
  	--Architecture
  	architecture solve of registro is
  	-- Signals,Constants,Variables,Components
  	begin
  	--Process #1
  	process(resetn,clk)
  	--Sequential programming
  	begin
  	if resetn='0' then
  	q<=(others => '0');
  	elsif clk'event and clk='1' then
  	if en='1' then
  	q<=d;
  	end if;
  	end if;
  	end process;
  	--Process #n...
  	end solve;

  view raw registro.vhd hosted with ❤ by GitHub

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