⭐⭐⭐⭐⭐ Maximum to minimum ordering of values in #RAM memory using #VHDL

• ➡️ #DigitalSystems #DigitalElectronic #DigitalCircuits #HDL #VHDL #FPGA

The following functional partition, which includes a Machine Sequential Synchronous (MSS), must perform a sorting of 255 values from Highest to Lowest. The entry of these 8-bit values must be done one by one, these values are entered through the "Data" port, while the data is being entered, the MSS sets high the "WritingData" output, indicating that this process is being executed and it will not end until the 255 values are completed. The ordering of the previously entered numbers should be done from highest to lowest, for which it is recommended to use the counter_up "j" and counter_up "i" in the search and comparison process. It is requested:

• Perform the functional partitioning
• Draw the ASM diagram of the MSS controller.
• Create in Quartus the Block diagram Schematic file
• Simulate the operation of the complete system in the VWF file.

Functional Partition

ASM Diagram

• ☑️ Repository with VHDL codes:
• https://github.com/vasanza/DigitalSystems/tree/main/Example_MaxToMin_ordering_in_RAM

• ☑️ Functional Partition PDF:
• https://github.com/vasanza/DigitalSystems/blob/main/Example_MaxToMin_ordering_in_RAM/2020_PAO2_2P_Examen(Resuelto).pdf

#VDHL Code by Angel Zumba

• sumador.vhd

• mss.vhd

• comparador.vhd

• contador_up.vhd

• mux2a1.vhd

• ram.vhd

• registro.vhd

Leer temas relacionados:

• ⭐ https://github.com/vasanza/DigitalSystems
• ⭐ https://github.com/vasanza/MSI_VHDL
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